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19-3297; Rev 0; 5/04
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers
General Description
The MAX3747/MAX3747A multirate limiting amplifiers function as data quantizers for OC-3 through OC-48 synchronous optical network (SONET), Fibre-Channel, and Gigabit Ethernet optical receivers. They are pin-for-pin compatible with the SY88993V from Micrel Semiconductor, Inc. The amplifiers accept a wide range of input voltages and provide constant-level, currentmode logic (CML) output voltages with controlled edge speeds. The MAX3747 output voltage level is 500mVp-p and the MAX3747A output voltage is 800mVp-p. The MAX3747/MAX3747A limiting amplifiers feature a programmable loss-of-signal detect (LOS) and an optional disable function (DISABLE). Output disable can be used to implement squelch. The MAX3747/MAX3747A are available in a 3mm, 10-pin MAX(R) package ideal for small form-factor receivers. 155Mbps to 3.2Gbps Operation >57dB of Gain for the MAX3747 and MAX3747A <10-12 BER with 2mVP-P Input Amplitude 18mA Supply Current Chatter-Free LOS with Programmable Threshold Output DISABLE Function PECL-Compatible Inputs
Features
Pin Compatible with Micrel SY88993V
MAX3747/MAX3747A
Ordering Information
PART TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 10 MAX 10 MAX PKG CODE U10C-4 U10C-4
Applications
Gigabit Ethernet SFP/SFF Optical Transceiver Modules 1G/2G Fibre-Channel SFP/SFF Optical Transceiver Modules Multirate OC-3 to OC-48 FEC SFP/SFF Optical Transceiver Modules 10G LX4 Transceiver Modules
SFP OPTICAL RECEIVER 3-INPUT DIAGNOSTIC MONITOR
DS1859
MAX3747EUB MAX3747AEUB
MAX is a registered trademark of Maxim Integrated Products, Inc. Pin Configuration appears at end of data sheet.
Typical Application Circuit
HOST BOARD SUPPLY FILTER VCC HOST FILTER VCC_RX
MAX4004
VCC 0.1F IN+ MAX3747 MAX3747A OUT+ 0.1F 50 0.1F 50 SERDES
MAX3745
0.1F
IN-
OUT-
5-PIN TO-HEADER 50 50 VREF TH GND LOS DISABLE 4.7k TO 10k VCC_HOST R1 0.1F R2 0.1F LOS
VCC
R1 + R2 5k
________________________________________________________________ Maxim Integrated Products
1
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155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +4.5V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at DISABLE, LOS, TH, VREF ..........-0.5V to (VCC + 0.5V) Current into LOS ...................................................-1mA to +9mA Current into VREF ..................................................................2mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ..............................................-25mA to +25mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 6.9mW/C above +70C) ...........552mW Operating Junction Temperature Range (TJ) .......-55C to +150C Storage Ambient Temperature Range (TS)...........-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50 to VCC, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise specified.) (Note 1)
PARAMETER POWER SUPPLY MAX3747 includes the CML output current Supply Current (Note 2) ICC MAX3747A includes the CML output current MAX3747/MAX3747A exclude the CML output current f < 2MHz (Note 3) (Note 3) 1200 42 DUT is powered on, f < 3GHz MAX3747A 4mVP-P VIN 1200mVP-P MAX3747 4mVP-P VIN 1200mVP-P AC-coupled outputs, VIN-MAX applied to the input (Note 4) 20% to 80% (Note 4) K28.5 pattern at 3.2Gbps PRBS 223 - 1 equivalent pattern at 2.7Gbps (Note 6) Deterministic Jitter (Notes 4, 5) DJ K28.5 pattern at 2.1Gbps PRBS 223 - 1 equivalent pattern at 155Mbps (Note 6) Random Jitter Input-Referred Noise Low-Frequency Cutoff VIN = 4mVP-P (Notes 4, 7) VIN = 4mVP-P (Note 4) 70 13.2 14 12 85 3.5 120 6.4 600 400 50 15 800 500 1000 600 15 120 19 25 17 150 5 150 psRMS VRMS kHz psP-P 58 30 36 18 30 4 35 41 24 dB mVP-P mVP-P dB mVP-P mVP-P ps mA SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Noise Rejection INPUT SPECIFICATION Input Sensitivity Input Overload OUTPUT SPECIFICATION Output Resistance Differential Output Return Loss CML Differential Output Voltage Differential Output Signal When Disabled Data-Output Transition Time TRANSFER CHARACTERISTIC
PSNR VIN-MIN VIN-MAX ROUT
2
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155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +3.63V, CML output load is 50 to VCC, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise specified.) (Note 1)
PARAMETER LOSS OF SIGNAL LOS Hysteresis LOS-Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level TTL/CMOS I/O VREF Voltage LOS Output High Voltage LOS Output Low Voltage DISABLE Input High DISABLE Input Low DISABLE Input Current VREF VOH VOL VIH VIL RLOS = 4.7k to 10k to VCC_HOST RLOS = 4.7k to 10k to VCC_HOST (3V) RLOS = 4.7k to 10k to VCC_HOST (3.6V) 2.0 0.8 10 VCC 1.35 2.4 0.4 VCC 1.3V VCC 1.19 V V V V V A 10log(VDEASSERT / VASSERT) (Note 4) (Notes 4, 8) VTH = -1.3V (Notes 4, 9) VTH = -1.3V (Notes 4, 9) VTH = -0.68V (Notes 4, 9) VTH = -0.68V (Notes 4, 9) VTH = -0.114V (Notes 4, 9) VTH = -0.114V (Notes 4, 9) 36.0 22 1.25 2.3 2.5 4.1 6.2 29 44.8 53.7 86 40.0 5.9 9.3 31 57 63.6 115 dB s mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3747/MAX3747A
Note 1: The data-input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below. The f-3db = 0.75 x 3.2GHz for a data rate of 3.2Gbps. Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1). Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude. Note 4: Guaranteed by design and characterization. Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification. Note 6: The PRBS 223 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros. Note 7: Random jitter was measured without using a filter at the input. Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2. Note 9: VTH is the voltage at pin 5 referenced to VCC (see Figure 5).
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3
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
VCC ICC (SUPPLY CURRENT) IOUT (CML OUTPUT CURRENT)
VIN SIGNAL ON 1dB MAXIMUM DEASSERT LEVEL
50
50
6dB
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL
0V
SIGNAL OFF
TIME
MAX3747 MAX3747A
Figure 1. Power-Supply Current Measurement
Figure 2. LOS Deassert Threshold--Set 1dB Below the Minimum by Receiver Sensitivity
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3747/MAX3747A toc01
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3747/MAX3747A toc02
3.2Gbps, 223 - 1 PRBS, 4mVP-P
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
60mV/div
60mV/div
50ps/div
50ps/div
4
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155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3747/MAX3747A toc03
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3747/MAX3747A toc04
OUTPUT EYE DIAGRAM AT +100C
MAX3747/MAX3747A toc05
2.7Gbps, 223 - 1 PRBS, 4mVP-P
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
2.125Gbps, CJTPAT, 50mVP-P
60mV/div
60mV/div
60mV/div
70ps/div
70ps/div
80ps/div
SUPPLY CURRENT vs. TEMPERATURE (EXCLUDES OUTPUT CURRENT)
MAX3747/MAX3747A toc06
TRANSFER FUNCTION (OUTPUT VOLTAGE vs. INPUT VOLTAGE)
MAX3747/MAX3747A toc07
RANDOM JITTER vs. TEMPERATURE
2.7 2.4 RANDOM JITTER (psRMS) 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 VIN = 50mVP-P, FREQ = 2.7Gbps
MAX3747/MAX3747A toc08
50 45 SUPPLY CURRENT (mA) 40 35 30 25 20 15 10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
1000 900 DIFFERENTIAL OUTPUT (mVP-P) 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 DIFFERENTIAL INPUT (mVP-P) MAX3747 MAX3747A
3.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
RANDOM JITTER vs. INPUT AMPLITUDE
3.2Gbps
MAX3747/MAX3747A toc09
BIT-ERROR RATIO vs. INPUT VOLTAGE
13,000 12,000 11,000 10,000 9000 8000 7000 6000 5000 4000 3000 2000 1000 1 0 1 MAXIM MAX3747
MAX3747/MAX3747A toc10
5
4 RANDOM JITTER (psRMS)
3
2
BIT-ERROR RATIO (10-12)
1
MICREL SY88993V
0 1 10 100 1000 10,000 DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
2
3
4
5
6
7
8
9
10
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
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5
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
DETERMINISTIC JITTER vs. INPUT AMPLITUDE
MAX3747/MAX3747A toc11
DETERMINISTIC JITTER vs. TEMPERATURE
35 DETERMINISTIC JITTER (ps) 30 25 20 15 10 5 VIN = 500mVP-P VIN = 5mVP-P FREQ = 3.2Gbps PATTERN = K28.5
MAX3747/MAX3747A toc12
25 3.2Gbps, K28.5 PATTERN DETERMINISTIC JITTER (psP-P) 20
40
15
10
5
0 1 10 100 1000 10,000 DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
ASSERT/DEASSERT vs. VTH
MAX3747/MAX3747A toc13
ASSERT/DEASSERT vs. TEMPERATURE
VTH = -1.1V, FREQ = 2.7Gbps PATTERN = PRBS 223 - 1
MAX3747/MAX3747A toc14
120 110 100 ASSERT/DEASSERT (mVP-P) 90 80 70 60 50 40 30 20 10 0
VTH (V) = VOLTAGE AT PIN 5 (V) WITH RESPECT TO VCC
40 35 ASSERT/DEASSERT (mV) 30 25 20 15 10 5
DEASSERT
DEASSERT
ASSERT
ASSERT
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
VTH (V)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C)
OUTPUT RETURN vs. FREQUENCY (SDD22) (INPUT SIGNAL LEVEL = -60dBm)
MAX3747/MAX3747A toc15
INPUT RETURN vs. FREQUENCY (SDD11) (INPUT SIGNAL LEVEL = -60dBm)
MAX3747/MAX3747A toc16
30 20 10 SDD22 (dB) 0 -10 -20 -30 100 1000 FREQUENCY (MHz)
30 20 10 SDD11 (dB) 0 -10 -20 -30
10,000
100
1000 FREQUENCY (MHz)
10,000
6
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155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers
Pin Description
PIN MAX3747/ MAX3747A NAME 1 2 3 4 5 6 7 8 9 10 DISABLE IN+ INVREF TH GND LOS OUTOUT+ VCC MICREL SY8893V NAME EN DIN DIN VREF LOSLVL GND LOS DOUT DOUT VCC Disable Function Pin. The data outputs are held static when this pin is asserted high, transistor-to-transistor logic (TTL). Noninverted Input Signal, CML Inverted Input Signal, CML Reference Voltage for LOS Threshold Setting Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets the threshold level. Connect one resistor from this pin to VCC and another from this pin to VREF (see Figure 5). Ground Loss-of-Signal, Open Collector. LOS is high when the level of the input signal drops below the preset threshold set by the TH input. LOS is deasserted low when the signal level is above the threshold. Inverted Data Output, CML Noninverted Data Output, CML Positive Power Supply FUNCTION
MAX3747/MAX3747A
Detailed Description
The limiting amplifiers consist of a multistage amplifier, offset-correction circuitry, an output buffer, and loss-ofsignal detect circuitry (see the Functional Diagram).
Input Stage
The input stage is shown in Figure 3. It provides 50 termination to VREF for each input signal, IN+ and IN-. The MAX3747/MAX3747A should be AC-coupled.
MAX3747 MAX3747A
VCC
Multistage Amplifier
The high-bandwidth multistage amplifier provides approximately 57dB of gain for the MAX3747 and 61dB of gain for the MAX3747A.
ESD STRUCTURES
Offset Correction Loop
The MAX3747/MAX3747A are susceptible to DC offsets in the signal path because they have high gain. In communication systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated in the transimpedance amplifier appears as an input offset and is reduced by the offset correction loop. The offset correction loop sets a low-frequency cutoff of 3.2kHz.
50
50 VREF
Figure 3. CML Input Stage _______________________________________________________________________________________ 7
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
Functional Diagram
VCC
MAX3747 MAX3747A
DIGITAL OFFSET CORRECTION IN+
50
50 OUT+ OUT-
IN-
50
50 VREF VREF VREF R1 SIGNAL DETECT TH LOS
DISABLE
R2
R1 + R2 5k
VCC
CML Output Buffer
The CML outputs of the MAX3747/MAX3747A limiting amplifiers provide high tolerance to impedance mismatches and inductive connectors. The output current is approximately 10mA for the MAX3747 and 16mA for the MAX3747A. Connecting the DISABLE pin to VCC disables the output. If the LOS pin is connected to the DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level drops below the LOS threshold. The output buffer can be AC- or DC-coupled to the load (Figure 4). The MAX3747 output is 500mVP-P and the MAX3747A output is 800mVP-P.
VCC
50
50 OUT+ OUT-
DISABLE
Q3
Q4
Q1
Q2 ESD STRUCTURES
DATA DISABLE DISABLE
Figure 4. CML Output Buffer
8
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155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers
Loss-of-Signal Indicator
The MAX3747/MAX3747A are equipped with LOS circuitry that indicates when the input signal is below a programmable threshold, set by a voltage on the TH pin (see the Typical Operating Characteristics). The voltage on the TH pin is set by two resistors, one connecting from the TH pin to VCC and the other connecting from TH to VREF (Figure 5). An RMS power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the LOS output, which is open collector. To prevent LOS chatter in the region of the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function. Once asserted, LOS is not deasserted until the input amplitude rises to the required level. Figure 6 shows the LOS output circuit.
VCC R1 TH R2 VREF
Applications Information
Program the LOS Assert Threshold
Program the LOS assert threshold according to Figure 5. The combination of R1 and R2 should be greater than or equal to 5k, see the Assert/Deassert vs. VTH graph in the Typical Operating Characteristics.
MAX3747/MAX3747A
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased: fIN = 1 / [2(50)(CIN)] For all applications, the recommended value for CIN and COUT is 0.1F, which provides fIN equal to 32kHz. Refer to Application Note HFAN-1.1: Choosing AC-Coupling Capacitors on the Maxim website (www.maxim-ic.com).
EMI Performance
The MAX3747/MAX3747A have been designed for better EMI performance. To help reduce EMI, special care has been taken to produce symmetrical signal outputs.
Pin Configuration
TOP VIEW
VTH = (R1 x (VREF - VCC)) / (R2 + R1) VTH IS VCC REFERENCED R1 + R2 5k DISABLE 1 IN+ INVREF
VCC
10 VCC 9 OUT+ OUTLOS GND
2 3 4 5
Figure 5. MAX3747/MAX3747A LOS Threshold Circuit
MAX3747 MAX3747A
8 7 6
TH
MAX
Chip Information
LOS
TRANSISTOR COUNT: 443 PROCESS: SiGe Bipolar
ESD STRUCTURE
Figure 6. MAX3747/MAX3747A LOS Output Circuit
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9
155Mbps to 3.2Gbps, Low-Power SFP Limiting Amplifiers MAX3747/MAX3747A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H 0 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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